The present invention relates to a computer system using a cache memory, and more particularly, to an apparatus and method for replacing cache line information by writing back the cache line information into a main memory and reading desired cache line information from the main memory.
A cache memory is used in a computer system for reducing the loss in system performance which occurs when accessing the main memory (usually DRAM) having a relatively low processing speed compared with the processing speed of a central processing unit (CPU) and a bus.
A cache memory is a high-speed buffer which is installed between the main memory and the CPU. The cache memory stores data of the area having a high frequency of use among the contents in a currently used main memory. Since the speed of the cache memory is five to ten times faster than that of the main memory, the effective memory access time can be reduced.
However, when a cache miss is generated because the desired data does not exist in the cache memory, or when sufficient space for storing new data does not exist in the cache memory, an operation cycle for replacing cached data in units of a cache line should be performed.
Such a cache line replacing operation cycle includes a write-back cycle and a read cycle. These write-back and read cycles, which are performed in connection with the main memory, significantly influence system performance.
FIGS. 1A and 1B show timing diagrams of a conventional cache line replacing operation cycle. All the processing procedures during the operation cycle occur in association with the main memory. Accordingly, the total timing of the operation cycle is dependent on the access latency of a DRAM memory which is used as the main memory. FIG. 1A shows addresses of a CPU/cache bus, and FIG. 1B shows data of the CPU/cache bus. In FIGS. 1A and 1B, the time periods designated by reference numerals 101 and 102 represent the access latency periods of the main memory, and the data designated as 1 to n represents the size of a cache line.
During a write-back cycle denoted by 103, data designated at 13 is written back according to a write-back address designated as 11 after the access latency period 101 of the main memory has elapsed, while during a read cycle denoted by 104, data designated at 14 is read according to a read address designated at 12 after the access latency period 102 of the main memory has elapsed.
As a result, the CPU begins the reading of desired data from the point denoted by "a" after performing the write-back cycle and the read cycle which are determined by the access latency of the main memory as shown in FIG. 1B.
To solve the problems associated with the cache line replacing operation cycle and improve the system performance, a high-speed write-back buffer is included in the cache line replacing apparatus. By doing so, when a cache miss occurs, the write-back data is stored in the buffer. This method is called a flagged register write-back (FRWB) method. As an example, a cache controller such as the commercially available Mercury Chipset number 82433LX from Intel Corporation can be used.
FIGS. 2A through 2D show timing diagrams of the cache line replacing cycle according to the conventional FRWB method. FIG. 2A shows addresses of the CPU/cache bus, FIG. 2B shows data of the CPU/cache bus, FIG. 2C shows addresses of the memory bus, and FIG. 2D shows data of the memory bus.
The operation cycle of the CPU/cache bus includes a cycle denoted by 201 during which write-back data designated at 23 is stored in a write-back buffer and another cycle denoted by 202 during which data designated at 27 of the memory bus is transferred to the CPU/cache bus. On the other hand, the operation cycle of the memory bus includes a cycle denoted by 205 during which data designated at 27 is read from the main memory through the memory bus and another cycle denoted by 206 during which data designated at 23 stored in the write-back buffer is written as data designated at 28 into the main memory.
The write-back data 23 is stored in the write-back buffer through the CPU/cache bus during cycle 201. Simultaneously, the main memory is accessed through the memory bus and the data 27 is read therefrom during cycle 205. Read cycle 202 of the CPU/cache bus begins irrespective of the access latency period of the main memory, immediately after the storage of the write-back data 23 has been completed. Accordingly, the CPU begins reading of the desired data from the point designated at "b" as shown in FIG. 2D. Data 23 which is stored in the write-back buffer is written back during cycle 206 from point "b" at which time the read cycle 202 of the CPU/cache bus has ended. Thus, a total operation cycle of the memory bus is completed at the time designated by point "c."
By reducing the time period needed due to the write-back cycle using a buffer rather than accessing the main memory through the CPU/cache bus during the write-back cycle 201, the CPU can more quickly read the desired data.
However, the time period designated at 203 which is needed for storing the data of the CPU/cache bus into the write-back buffer is generally longer than the access latency period of the main memory. Since the larger the size of the cache line, the longer the time required for storing the data, the cycle time cannot not be said to have been sufficiently reduced.
Also, write-back data 23 is stored in the write-back buffer during write-back cycle 201. Then, after read cycle 202 completes at point "c," the data of the write-back buffer is actually written back into the main memory. As a result, the memory bus-occupied time period of cycles 205 and 206 during the cache line replacing cycle increase by the difference between the required buffering time and the access latency period of the main memory, and becomes longer than the total time of cycle 103 plus cycle 104 shown in FIG. 1B.
Thus, since the memory bus has a maximum data transmission limit, since loss of the bandwidth which occupies the memory bus occurs. Particularly, various processors in a multi-processor system commonly occupy a single memory bus, the memory bus bandwidth becomes one of the most important system performance parameters.